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HYMD264G726CL4M-M Datasheet(PDF) 9 Page - Hynix Semiconductor

Part # HYMD264G726CL4M-M
Description  Low Profile Registered DDR SDRAM DIMM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HYMD264G726CL4M-M Datasheet(HTML) 9 Page - Hynix Semiconductor

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HYMD264G726C(L)4M-M/K/H/L
Rev. 0.1 / Mar. 2003
9
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR266(2-2-2)
DDR266A
DDR266B
DDR200
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
60
-
65
-
65
-
70
-
ns
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
45
120K
45
120K
45
120K
50
120K
ns
Active to Read with Auto
Precharge Delay
tRAP
15
-
20
-
20
-
20
-
ns
16
Row Address to Column Address
Delay
tRCD
15
-
20
-
20
-
20
-
ns
Row Active to Row Active Delay
tRRD
15
-
15
-
15
-
15
-
ns
Column Address to Column
Address Delay
tCCD
1-
1
-
1
-
1
-
CK
Row Precharge Time
tRP
15
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
ns
Write to Read Command Delay
tWTR
1-
1
-
1
-
1
-
CK
Auto Precharge Write Recovery
+ Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-CK
15
System Clock
Cycle Time
CL = 2.5
tCK
7.5
12
7.5
12
7.5
12
8.0
12
ns
CL = 2
7.5
12
7.5
12
10
12
10
12
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge
Skew
tAC
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Clock edge
Skew
tDQSCK
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.5
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-ns
1, 10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-ns
1,9
Data Hold Skew Factor
tQHS
-
0.75
-
0.75
-
0.75
-
0.75
ns
10
Valid Data Output Window
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
Data-out high-impedance
window from CK, /CK
tHZ
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
17
Data-out low-impedance window
from CK, /CK
tLZ
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
17


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