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HYMD264M646BLF8-M Datasheet(PDF) 10 Page - Hynix Semiconductor |
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HYMD264M646BLF8-M Datasheet(HTML) 10 Page - Hynix Semiconductor |
10 / 19 page HYMD264M646B(L)F8-J/M/K/H/L Rev. 0.2 / Apr. 2004 10 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) <DDR333, DDR266(2-2-2)> Parameter Symbol DDR333 DDR266(2-2-2) Unit Note Min Max Min Max Row Cycle Time tRC 60 - 60 - ns Auto Refresh Row Cycle Time tRFC 72 - 75 - ns Row Active Time tRAS 42 70K 45 120K ns Active to Read with Auto Precharge Delay tRAP 18 - 15 - ns 16 Row Address to Column Address Delay tRCD 18 - 15 - ns Row Active to Row Active Delay tRRD 12 - 15 - ns Column Address to Column Address Delay tCCD 1- 1 - CK Row Precharge Time tRP 18 - 15 - ns Write Recovery Time tWR 15 - 15 - ns Write to Read Command Delay tWTR 1- 1 - CK Auto Precharge Write Recovery + Precharge Time tDAL (tWR/tCK) + (tRP/tCK) - (tWR/tCK) + (tRP/tCK) -CK 15 System Clock Cycle Time CL = 2.5 tCK 6 12 7.5 12 ns CL = 2 7.5 12 7.5 12 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.7 0.7 -0.75 0.75 ns DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 -0.75 0.75 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.4 - 0.5 ns Data-Out hold time from DQS tQH tHP -tQHS - tHP -tQHS -ns 1, 10 Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) -ns 1,9 Data Hold Skew Factor tQHS -0.6 - 0.75 ns 10 Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ ns Data-out high-impedance window from CK, /CK tHZ -0.7 0.7 -0.75 0.75 ns 17 Data-out low-impedance window from CK, /CK tLZ -0.7 0.7 -0.75 0.75 ns 17 Input Setup Time (fast slew rate) tIS 0.75 - 0.9 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.75 - 0.9 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 0.8 - 1.0 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 0.8 - 1.0 - ns 2,4,5,6 Input Pulse Width tIPW 2.2 2.2 ns 6 Write DQS High Level Width tDQSH 0.35 - 0.35 - CK |
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