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HYMD132645BL8J-J Datasheet(PDF) 8 Page - Hynix Semiconductor |
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HYMD132645BL8J-J Datasheet(HTML) 8 Page - Hynix Semiconductor |
8 / 16 page Rev. 0.1/Jun. 02 8 HYMD132645B(L)8J-J DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition Speed Unit Note -J Operating Current IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1040 mA Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length= 2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 1200 mA Precharge Power Down Standby Current IDD2P All banks idle; Power down mode ; CKE=Low, tCK=tCK(min) 320 mA Idle Standby Current IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM 640 mA Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 320 mA Active Standby Current IDD3N /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 640 mA Operating Current IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT = 0mA 2160 mA Operating Current IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle 2160 mA Auto Refresh Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 1600 mA Self Refresh Current IDD6 CKE =< 0.2V; External clock on; tCK=tCK(min) Normal 32 mA Low Power 16 mA Operating Current - Four Bank Operation IDD7 Four bank interleaving with BL=4, Refer to the following page for detailed test condition 2720 mA |
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