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H5GQ1H24AFR Datasheet(PDF) 8 Page - Hynix Semiconductor |
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H5GQ1H24AFR Datasheet(HTML) 8 Page - Hynix Semiconductor |
8 / 173 page This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 8 H5GQ1H24AFR 0.2. CLOCKING The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 uses a DDR data interface and an 8n‐prefetch architecture. The data interface uses two differen‐ tial forwarded clocks (WCK/WCK#). DDR means that the data is registered at every rising edge of WCK and rising edge of WCK#. WCK and WCK# are continuously running and operate at twice the frequency of the command/address clock (CK/CK#). Figure 1: GDDR5 Clocking and Interface Relationship CK CK# COMMAND ADDRESS DQ*1 WCK WCK# Note : Figure.1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram. |
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