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H5MS1G32MFP-L3M Datasheet(PDF) 3 Page - Hynix Semiconductor

Part # H5MS1G32MFP-L3M
Description  1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5MS1G32MFP-L3M Datasheet(HTML) 3 Page - Hynix Semiconductor

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Rev 1.2 / Jun. 2008
3
Mobile DDR SDRAM 1Gbit (32M x 32bit)
H5MS1G22MFP Series / H5MS1G32MFP Series
FEATURES SUMMARY
● Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
● Mobile DDR SDRAM INTERFACE
- x32 bus width
- Multiplexed Address (Row address and Column ad-
dress)
● SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
● MEMORY CELL ARRAY
- 1Gbit (x32 device) = 8M x 4Bank x 32 I/O
● DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
● LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
● INPUT CLOCK
- Differential clock inputs (CK, CK)
● Data MASK
- DM0 ~ DM3: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
● MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
● CAS LATENCY
- Programmable CAS latency 2 or 3 supported
● BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
● AUTO PRECHARGE
- Option for each burst access
● AUTO REFRESH AND SELF REFRESH MODE
● CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
● INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
● Operation Temperature
- -30
oC ~ 85oC
● PACKAGE
- 90 Ball Lead Free FBGA
● ADDRESS TABLE
Note)Reduced Page size:16,384 rows by 512 columns by 32 bits.
Part Number
Page Size
Row
Address
Column
Address
H5MS1G22MFP
4KByte
A0 ~ A12
A0 ~ A9
H5MS1G32MFP1)
2KByte
A0 ~ A13
A0 ~ A8


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