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H5MS1G32MFP-L3M Datasheet(PDF) 4 Page - Hynix Semiconductor

Part # H5MS1G32MFP-L3M
Description  1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5MS1G32MFP-L3M Datasheet(HTML) 4 Page - Hynix Semiconductor

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Rev 1.2 / Jun. 2008
4
Mobile DDR SDRAM 1Gbit (32M x 32bit)
H5MS1G22MFP Series / H5MS1G32MFP Series
DESCRIPTION
The Hynix H5MS1G(2/3)2MFP Series is 1,073,741,824-bit CMOS Low Power Double Data Rate Synchronous DRAM
(Mobile DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of
8,388,608 x32.
The HYNIX H5MS1G(2/3)2MFP series uses a double-data-rate architecture to achieve high-speed operation. The dou-
ble data rate architecture is essentially a 2
n prefetch architecture with an interface designed to transfer two data per
clock cycle at the I/O pins.
The Hynix H5MS1G(2/3)2MFP Series offers fully synchronous operations referenced to both rising and falling edges of
the clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates
from a differential clock
: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK),
data, data strobe and data mask inputs are sampled on both rising and falling edges of it (
Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). The data
paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible
with LVCMOS.
Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-
istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and the starting column location
for the burst access.
The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)
allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
times.
The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which
are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.
A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on
any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-
bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be
used for Read with Autoprecharge enabled and for Write bursts.


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