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H5MS1222EFP-J3M Datasheet(PDF) 8 Page - Hynix Semiconductor |
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H5MS1222EFP-J3M Datasheet(HTML) 8 Page - Hynix Semiconductor |
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8 / 62 page  Rev 1.0 / Jun. 2008 8 Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series Mobile DDR SDRAM PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CK, CK INPUT Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE INPUT Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. CS INPUT Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE (along with CS) define the command being entered BA0, BA1 INPUT Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA0 and BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR). A0 ~ A11 INPUT Address inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a MODE REGISTER SET command. A10 sampled during a PRECHARGE command deter- mines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. For 128Mb (x32), Row Address: A0 ~ A11, Column Address: A0 ~ A7 Auto-precharge flag: A10 DQ0 ~ DQ31 I/O Data Bus: data input / output pin DM0 ~ DM3 INPUT Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ and DQS loading. For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31. DQS0 ~ DQS3 I/O Data Strobe: Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. Used to capture write data. For x32 device, DQS0 corre- sponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 cor- responds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31. VDD SUPPLY Power supply VSS SUPPLY Ground VDDQ SUPPLY I/O Power supply VSSQ SUPPLY I/O Ground NC - No Connect: No internal electrical connection is present. |
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Similar Description - H5MS1222EFP-J3M |
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