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H5MS1222EFP-J3M Datasheet(PDF) 9 Page - Hynix Semiconductor |
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H5MS1222EFP-J3M Datasheet(HTML) 9 Page - Hynix Semiconductor |
9 / 62 page Rev 1.0 / Jun. 2008 9 Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 32 I/O Mobile DDR SDRAM 32 Address Register Mode Register Bank Select Row Active CAS Latency CLK CKE /CS /RAS /CAS /WE DM0 ~DM3 A0 A1 BA1 BA0 A11 PASR Refresh DQ0 DQ31 Column decoders 1Mx32 Bank0 1Mx32 Bank1 1Mx32 Bank2 1Mx32 Bank3 Memory Cell Array Data Out Control /CLK DS 64 32 64 Data Strobe Transmitter Data Strobe Receiver DS DQS0 ~ DQS3 Extended Mode Register Self refresh logic & timer Internal Row Counter Write Data Register 2-bit Prefetch Unit Row Pre Decoder Column Pre Decoder Column Add Counter Burst Counter Column Active |
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