H55S5162DFR-75M datasheet(5/55 Pages) HYNIX

Part #	H55S5162DFR-75M

Description	512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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5 / 55 page

Rev 1.5 / Feb. 2009

5

11

512Mbit (32Mx16bit) Mobile SDR Memory

H55S5162DFR Series

FEATURES

●

Standard SDRAM Protocol

●

Clock Synchronization Operation

- All the commands registered on positive edge of basic input clock (CLK)

●

MULTIBANK OPERATION - Internal 4bank operation

- During burst Read or Write operation, burst Read or Write for a different bank is performed.

- During burst Read or Write operation, a different bank is activated and burst Read or Write

for that bank is performed

- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed

●

Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V

●

LVCMOS compatible I/O Interface

●

Low Voltage interface to reduce I/O power

●

Programmable burst length: 1, 2, 4, 8 or full page

●

Programmable Burst Type: sequential or interleaved

●

Programmable CAS latency of 3 or 2

●

Programmable Drive Strength

●

Low Power Features

- Programmable PASR(Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Programmable DS (Drive Strength)

- Deep Power Down Mode

●

Operation Temperature

- Mobile Temp.: -30

oC ~ 85oC

●

Package Type: 54ball FBGA, 0.8mm pitch, 8 x 8 [mm2], t=1.0mm max, Lead & Halogen Free

512M SDRAM ORDERING INFORMATION

Part Number

Clock

Frequency

Temperature

CAS

Latency

Organization

Interface

54Ball

FBGA

H55S5162DFR-60M

166MHz

Mobile Temp.

-30

oC ~ 85oC

3

4banks x 8Mb x 16

LVCMOS

Lead &

Halogen

Free

H55S5162DFR-75M

133MHz

H55S5162DFR-A3M

105MHz

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H55S5162DFR-75M Datasheet(PDF) 5 Page - Hynix Semiconductor

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