Rev 1.0 / Aug. 2009

6

111

Synchronous DRAM Memory 256Mbit

H57V2562GTR Series

54_TSOPII Pin DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

CLK

INPUT

Clock :

The system clock input. All other inputs are registered to the SDRAM on the rising edge

of CLK

CKE

INPUT

Clock Enable:

Controls internal clock signal and when deactivated, the SDRAM will be one of the states

among power down, suspend or self refresh

CS

INPUT

Chip Select:

Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1

INPUT

Bank Address:

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A12

INPUT

Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8

Auto-precharge flag: A10

RAS, CAS, WE

INPUT

Command Inputs:

RAS, CAS and WE define the operation

Refer function truth table for details

LDQM, UDQM

I/O

Data Mask:

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15

I/O

Data Input / Output:

Multiplexed data input / output pin

SUPPLY

Power supply for internal circuits and input buffers

SUPPLY

Power supply for output buffers

NC

-

No connection : These pads should be left unconnected