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HY5FS123235AFCP-07 Datasheet(PDF) 5 Page - Hynix Semiconductor |
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HY5FS123235AFCP-07 Datasheet(HTML) 5 Page - Hynix Semiconductor |
5 / 74 page Rev. 1.2 /June. 2008 5 HY5FS123235AFCP FEATURES • Double-data rate architecture; two data transfers per clock cycle • Single ended READ strobe (RDQS) per byte • Single ended WRITE strobe (WDQS) per byte • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge; data and data mask referenced to both edges of RDQS/WDQS • Eight internal banks for concurrent operation • Data mask (DM) for masking WRITE data • Burst Length: 8 only • Multiplexed addressing • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • On die termination (ODT) • Calibrated output drive • Programmable offset for both driver and termination • POD_18 compatible inputs/outputs • VDD and VDDQ: 1.8V +/- 5%, 2.0V +/- 5% • CAS Latency : 7~22 FUNCTIONAL DESCRIPTION The Hynix HY5FS123235AFCP is a high speed CMOS, dynamic random access memory internally configured as a eight bank DRAM. These devices contain the following number of bits: 512M has 536,870,912 bits and eight banks The Hynix HY5FS123235AFCP uses a double data rate architecture to achieve high speed operation. Thedoubledataratearchitectureisessentially an 8N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix HY5FS123235AFCP effectively consists of an 8N data transfer every four clock-cycles at the inernal DRAM core and eight corresponding n-bit wide, one-half- clock-cycle data transfers at the I/O pins. Uni-directional data strobes are transmitted externally, along with data, for use in data capture at the receiver. RDQS is a strobe transmitted by the GDDR4 SDRAM during READs. WDQS is the data strobe sent by the memory controller during WRITEs. RDQS is edge aligned with data for READs and WDQS is center aligned with data for WRITEs. The GDDR4 SDRAM operates from a differential clock (CK and CK# the crossing of the CK going high and CK# going low will be referred to as the positive edge of CK). Commands (address and control signals) are registered at the positive edge of CK. Address is received on two consecutive rising edges of CK. Input data is registered at both edges of WDQS, and output data is referenced to both edges of RDQS, as well as to both edges of CK. Read and write accesses to the GDDR4 SDRAM are burst oriented; accesses start at a selected location and continue for a total of eight locations. Accesses begi n with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column locaion for the burst access. ORDERING INFORMATION Note: Above Hynix P/N’s and their homogeneous Subcomponents are RoHS(& Lead free) Compliant. Part No. Power Supply Clock Frequency Max Data Rate Interface HY5FS123235AFCP-06 VDD/VDDQ = 2.0V 1.6GHz 3.2Gbps/pin POD_18 HY5FS123235AFCP- 07 1.4GHz 2.8Gbps/pin HY5FS123235AFCP- 08 VDD/VDDQ = 1.8V 1.2GHz 2.4Gbps/pin HY5FS123235AFCP- 09 1.1GHz 2.2Gbps/pin |
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