Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

HY5PS12421AFP-S6 Datasheet(PDF) 8 Page - Hynix Semiconductor

Part # HY5PS12421AFP-S6
Description  512Mb DDR2 SDRAM
Download  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5PS12421AFP-S6 Datasheet(HTML) 8 Page - Hynix Semiconductor

Back Button HY5PS12421AFP-S6 Datasheet HTML 4Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 5Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 6Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 7Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 8Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 9Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 10Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 11Page - Hynix Semiconductor HY5PS12421AFP-S6 Datasheet HTML 12Page - Hynix Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 37 page
background image
Rev. 0.2 / Mar. 2005
8
512Mb A-ver. DDR2 SDRAM
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank).
CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asyn-
chronous for SELF REFRESH exit. After VREF has become stable during the power on and initial-
ization sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high
throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled
during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CS
Input
Chip Select : All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
ODT
Input
On Die Termination Control : ODT(registered HIGH) enables on die termination resistance inter-
nal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS, RDQS,
and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/
UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode
Register(EMRS(1)) is programmed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(LDM, UDM)
Input
Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is
sampled High coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS command.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE
command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also deter-
mines if the mode register or extended mode register is to be accessed during a MRS or EMRS
cycle.
A0 -A15
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge command to determine
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the
op code during MODE REGISTER SET commands.
DQ
Input/
Output
Data input / output : Bi-directional data bus
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/
Output
Data Strobe : Output with read data, input with write data. Edge aligned with read data, cen-
tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds
to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in
single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS
to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1)
control bit enables or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of
EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
x8 DQS/DQS, RDQS/RDQS,
if EMRS(1)[A11] = 1
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of
EMRS(1)
x4 DQS
x8 DQS
if EMRS(1)[A11] = 0
x8 DQS, RDQS,
if EMRS(1)[A11] = 1
x16 LDQS and UDQS


Similar Part No. - HY5PS12421AFP-S6

ManufacturerPart #DatasheetDescription
logo
Hynix Semiconductor
HY5PS12421BFP-C4 HYNIX-HY5PS12421BFP-C4 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
HY5PS12421BFP-E3 HYNIX-HY5PS12421BFP-E3 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
HY5PS12421BFP-S5 HYNIX-HY5PS12421BFP-S5 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
HY5PS12421BFP-S6 HYNIX-HY5PS12421BFP-S6 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
HY5PS12421BFP-Y4 HYNIX-HY5PS12421BFP-Y4 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
More results

Similar Description - HY5PS12421AFP-S6

ManufacturerPart #DatasheetDescription
logo
Hynix Semiconductor
H5PS5162FFR-C HYNIX-H5PS5162FFR-C Datasheet
530Kb / 39P
   512Mb DDR2 SDRAM
HY5PS12421F HYNIX-HY5PS12421F Datasheet
623Kb / 35P
   512Mb DDR2 SDRAM
HY5PS12421FP HYNIX-HY5PS12421FP Datasheet
622Kb / 35P
   512Mb DDR2 SDRAM
H5PS5182GFR HYNIX-H5PS5182GFR Datasheet
1Mb / 64P
   512Mb DDR2 SDRAM
logo
Nanya Technology Corpor...
NT5TU64M8EE NANYA-NT5TU64M8EE Datasheet
3Mb / 96P
   DDR2 512Mb SDRAM
logo
Hynix Semiconductor
HY5PS12421F-E3 HYNIX-HY5PS12421F-E3 Datasheet
1Mb / 35P
   512Mb DDR2 SDRAM
HY5PS12421CFP-E3I HYNIX-HY5PS12421CFP-E3I Datasheet
618Kb / 38P
   512Mb DDR2 SDRAM
HY5PS12421CFP-E3 HYNIX-HY5PS12421CFP-E3 Datasheet
619Kb / 38P
   512Mb DDR2 SDRAM
H5PS5162FFR-E3 HYNIX-H5PS5162FFR-E3 Datasheet
530Kb / 39P
   512Mb DDR2 SDRAM
HY5PS12421BFP-E3 HYNIX-HY5PS12421BFP-E3 Datasheet
628Kb / 38P
   512Mb DDR2 SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com