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VG3617161ET-6 Datasheet(PDF) 6 Page - Vanguard International Semiconductor |
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VG3617161ET-6 Datasheet(HTML) 6 Page - Vanguard International Semiconductor |
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6 / 69 page  Document:1G5-0189 Rev.1 Page 6 VIS VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM A.C Characteristics: (6)(7)(8)(10) (VDD=3.3V , VSS=0V, Ta=0 to 70°C) Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. 4. These parameters depend on the output loading. Specified values are obtained with the outputs open. 5. Assume minimum column address update cycle tCCD (min). Symbol A.C. Parameter -6 -7 -8 Unit Note Min Max Min Max Min Max tCH Clock high time 2.5 2.5 3 ns tCL Clock low time 2.5 2.5 3 tT Transition time (Rise and Fall) 0.5 10 0.5 10 0.5 10 tCK3 Clock cycle time CL* = 3 6 7 8 tCK2 CL* = 2 8 10 12 tIS Address/Control Input setup time 1.5 1.75 2 tIH Address/Control Input hold time 1 1 1 tDS Data Input setup time 1.5 1.75 2 tDH Data Input hold time 1 1 1 tLZ Data output low impedance 1 1 1 tHZ3 Data output high imped- ance CL* = 3 5.5 5.5 6 9 tHZ2 CL* = 2 6 7 7 9 tAC3 Access time from CLK (positive edge) CL* = 3 5.5 6 6 tAC2 CL* = 2 6 7 7 tOH Data output hold time 2.3 2.5 2.5 tRCD RAS to CAS delay 18 20 20 tRRD Row activate to row activate delay 12 14 16 tCCD CAS to CAS Delay time 1 1 1 CLK tDPL Last data in to precharge 2 2 2 CLK tRAS Row activate to precharge time 36 100,000 42 100,000 48 100,000 ns tRP Precharge to refresh/row activate command 3 3 3 CLK tDAL3 Data-in to ACT (REF) Command (CL = 3) 5 5 5 CLK tDAL2 Data-in to ACT (REF) Command (CL = 2) 5 5 5 CLK tRC Row cycle time 54 63 72 ns tRSC Mode Register Set Cycle time 2 2 2 CLK tREF Refresh time 64 64 64 ms tSRX Minimum CKE ”High”for Self-Refresh exit 1 1 1 CLK tBDL Last data in to burst STOP command 1 1 1 CLK tPDE Power Down Exit set-up time 1 1 1 CLK 0.3V ± |
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