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MAX9951DCCB+TD Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX9951DCCB+TD Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 24 page Dual Per-Pin Parametric Measurement Units _______________________________________________________________________________________ 7 Note 2: The device operates properly with different supply voltages with equally different voltage swings. Note 3: Interpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point-to-end-point range, i.e., for the ±64mA range, the full-scale range = 128mA, and a 1% error = 1.28mA. Note 4: Case must be maintained ±5°C for linearity specifications. Note 5: Tested in range C. Note 6: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled. Note 7: Specified as the percent of full-scale range change at the output per volt change in the DUT voltage. Note 8: VCLLO_ and VCLHI_ should differ by at least 700mV. Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at VL adjusts the threshold. Note 10: Guaranteed by design. Note 11: Settling times are to 0.1% of FSR. Cx_ = 60pF. Note 12: All settling times are specified using a single compensation capacitor (Cx_) across all current-sense resistors. Use an indi- vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges. Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by holding VSENSE_ steady and transitioning THMAX_ or THMIN_. Note 14: Maximum serial clock frequency may diminish at VL < +3.3V. AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +12V, VEE = -7V, VL = +3.3V, CCM = 120pF, CL = 100pF, TA = +25°C, unless otherwise noted. Specifications at TA = TMIN and TA = TMAX are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Fall to DOUT Valid tDO 22 ns CS Low to SCLK High Setup tCSS0 10 ns SCLK High to CS High Hold tCSH1 22 ns SCLK High to CS Low Hold tCSH0 0ns CS High to SCLK High Setup tCSS1 5ns DIN to SCLK High Setup tDS 10 ns DIN to SCLK High Hold tDH (Note 13) 0 ns CS Pulse-Width High tCSWH 10 ns CS Pulse-Width Low tCSWL 10 ns LOAD Pulse-Width Low tLDW 20 ns VDD High to CS Low (Power-Up) (Note 13) 500 ns |
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