ADS1259 datasheet(6/45 Pages) TI

Part #	ADS1259

Description	Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter with Low-Drift Reference

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Manufacturer	TI [Texas Instruments]

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SCLK

CS

DIN

DOUT

t

SCLK

t

CSSC

t

DIHD

t

CSH

t

CSDOD

t

DIST

t

SPWH

t

SPWL

t

CSDOZ

t

DOHD

t

DOPD

B7

B6

B5

B4

B3

B2

B1

B0

B7

B6

B5

B4

B3

B2

B1

B0

ADS1259

SBAS424C – JUNE 2009 – REVISED MARCH 2010

www.ti.com

SPI TIMING CHARACTERISTICS

Figure 1. Serial Interface Timing

TIMING REQUIREMENTS: SERIAL INTERFACE TIMING

At TA = –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

tCSSC

CS low to first SCLK: setup time(1)

50

ns

tSCLK

SCLK period

1.8

tCLK

(2)

tSPWH

SCLK pulse width: high

90

ns

90

ns

tSPWL

SCLK pulse width: low(3)

216

tCLK

tDIST

Valid DIN to SCLK falling edge: setup time

35

ns

tDIHD

Valid DIN to SCLK falling edge: hold time

20

ns

tDOPD

SCLK rising edge to valid new DOUT: propagation delay(4)

60

ns

tDOHD

SCLK rising edge to DOUT invalid: hold time

0

ns

tCSDOD

CS low to DOUT driven: propagation delay(4)

0

40

ns

tCSDOZ

CS high to DOUT Hi-Z: propagation delay

20

ns

tCSH

CS high pulse

20

tCLK

(1)

CS can be tied low.

(2)

tCLK = 1/fCLK.

(3)

Holding SCLK low longer than 216 × tCLK cycles resets the SPI interface (enabled by SPI register bit).

(4)

DOUT load = 20pF || 100k

Ω to DGND.

6

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