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SLUS893 – MARCH 2010

PIN FUNCTIONS

PIN

FUNCTION DESCRIPTION

NO.

NAME

1

VCC

IC power positive supply. Connect, through a 10

Ω resistor to the common-source (diode-OR) point: source of

high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10

Ω

resistor to the cathode of the input diode. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.

2

CE

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1M

Ω pull-down

resistor.

3

STAT

Open-drain charge status pin to indicate various charger operation (See Table 3)

4

TS

Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot

and cold temperature window with a resistor divider from VREF to TS to GND.

5

PG

Open-drain power-good status output. The transistor turns on when a valid VCC is detected. It is turned off in the

sleep mode. PG can be used to drive a LED or communicate with a host processor. It can be used to drive ACFET

and BATFET.

6

VREF

3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage

could be used for programming of voltage and current regulation and for programming the TS threshold.

7

ISET

Charge current set input. The voltage of ISET pin programs the charge current regulation, pre-charge current and

termination current set-point.

8

VFB

Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery

terminals to this node to adjust the output battery regulation voltage.

9

SRN

Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode

filtering.

10

SRP

Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.

11

GND

Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.

12

REGN

PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to PGND pin, close to

the IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from

REGN to BTST.

13

LODRV

PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

14

PH

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1mF bootstrap capacitor from PH to

BTST.

15

HIDRV

PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

16

BTST

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1mF bootstrap capacitor from SW to

BTST

PowerPad

Exposed pad beneath the IC. Always solder PowerPad to the board, and have vias on the PowerPad plane

star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to

dissipate the heat.

Copyright © 2010, Texas Instruments Incorporated

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