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TPS92002D Datasheet(PDF) 6 Page - Texas Instruments |
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TPS92002D Datasheet(HTML) 6 Page - Texas Instruments |
6 / 14 page ( ) ( ) ( ) - = ´ + ´ + 1 OSC CT RTC RTD f 0.74 C 27pF R R ( ) = ´ ´ + ´ MAX TC T OSC D 0.74 R C 27pF f + – + – S Q R Q2 Q1 3 4 R RTD C CT R RTC V REF 3.33 V 1.67 V CLK Oscillator Oscillator Latch UDG-10005 RTC RTD TPS92001, TPS92002 SLUSA24 – FEBRUARY 2010 www.ti.com APPLICATION INFORMATION Introduction The typical application diagrams in Figure 3 and Figure 4 show isolated and non-isolated flyback converters utilizing the TPS92001. Note that the capacitors CREF and CVDD are local decoupling capacitors for the reference and device input voltage, respectively. Both capacitors should be low ESR and ESL ceramic, placed as close as possible to the device pins, and returned directly to the ground pin of the device for best stability. The REF pin provides the internal bias to many of the device functions and CREF should be at least 0.47-µF to prevent the REF voltage from drooping. Current Sense (CS) Pin In the TPS92001/2, the current regulation is obtained through the summation of the primary current sense and any slope compensation at the CS pin compared to a 1-V threshold, as shown in the FUNCTIONAL BLOCK DIAGRAM. Crossing this 1-V threshold resets the PWM latch and modulates the output driver on-time. In the absence of a CS signal, the output obeys the programmed maximum on-time of the oscillator. When adding slope compensation, it is important to use a small capacitor to AC couple the oscillator waveform before summing this signal into the CS pin. By forcing the CS node to exceed the 1-V threshold the TPS92001/2 is forced to zero percent duty cycle. Oscillator Equation 3 calculates the oscillator frequency setting. (3) (4) Referring to Figure 1 and the waveforms in Figure 2, when Q1 is on, CCT charges via the on-resistance of the Q1 MOSFET and the RTC pin. During this charging process, the voltage of CCT is sensed through the RTD pin. The S input of the oscillator latch, SOSC, is level sensitive, so crossing the upper threshold (set at 2/3 VREF or 3.33 V for a typical 5.0 V reference) sets the Q output (CLK signal) of the oscillator latch high. A high CLK signal results in turning off Q1 and turning on Q2. The timing capacitor then discharges through RTD and the RDS(on) of Q2. CCT discharges from 3.33 V to the lower threshold (set at 1/3 REF or 1.67 V for a typical 5.0-V reference) sensed through RTC. The R input to the oscillator latch, ROSC, is also level sensitive and resets the CLK signal low when CCT crosses the 1.67-V threshold, turning off Q2 and turning on Q1, initiating another charging cycle. Figure 1. Oscillator Function 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS92001 TPS92002 |
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