Technical Note

4/7

BD47□□G series

www.rohm.com

2010.01 - Rev.B

© 2010 ROHM Co., Ltd. All rights reserved.



Explanation of Operation

BD47□□G series has the detection voltages and release voltages as threshold voltages and, as the voltages applied to the

input reach their respective threshold voltages, the output switches from “High” to “Low” and from “Low” to “High”. The

release voltage has a hysteresis that is the detection voltage +50mV (Typ.), preventing chattering in the output. When the

input is greater than the release voltage, the output is in a “High” state. When the input is lowered from that state, the output

switches to “Low” on the detection voltage. When the input is less than the detection voltage, the output is in a “Low” state.

When the input is raised from that state, the output switches to “High” with the release voltage. Additionally, at least 0.85V is

required for the circuit to operate fully. When the input falls below the operating limit voltage, the output becomes unsettled.

1

When the power supply is turned on, the output is unsettled from after over the operating limit voltage (VOPL) until

TPHL. There fore it is possible that the reset signal is not outputted when the rise time of VDD is faster than TPHL.

2

When VDD is greater than VOPL but less than the reset release voltage (VS + ΔVS), the output voltages will switch to

Low.

3

If VDD exceeds the reset release voltage (VS + ΔVS), then VOUT switches from L to H.

4

If VDD drops below the detection voltage (VS) when the power supply is powered down or when there is a power

supply fluctuation, VOUT switches to L (with a delay of TPHL).

5

The potential difference between the detection voltage and the release voltage is known as the hysteresis width (ΔVS).

The system is designed such that the output does not flip-flop with power supply fluctuations within this hysteresis width,

preventing malfunctions due to noise.

<Precautions>

Please be aware that when there is resistance on the power supply line, the detection voltage varies with voltage drops

caused by the IC current consumption.

Please connect a capacitor between VCC and GND when the power supply line has high impedance.

0V

①

②

③

④

⑤

Fig.11 Timing Waveform