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BD5235 Datasheet(PDF) 5 Page - Rohm |
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BD5235 Datasheet(HTML) 5 Page - Rohm |
5 / 10 page Technical Note 5/9 BD52 □□G, BD52□□FVE, BD53□□G, BD53□□FVE series www.rohm.com 2009.06 - Rev.B © 2009 ROHM Co., Ltd. All rights reserved. Setting of Detector Delay Time This detector IC can be set delay time at the rise of VDD by the capacitor connected to CT terminal. Delay time at the rise of VDD TPLH:Time until when Vout rise to 1/2 of VDD after VDD rise up and beyond the release voltage(VDET+∆VDET) TPLH = -CCT×RCT×ln CCT: CT pin Externally Attached Capacitance RCT : CT pin Internal Impedance (P.2 RCT refer.) VCTH: CT pin Threshold Voltage(P.2 VCTH refer.) Ln : Natural Logarithm Reference Data of Falling Time (TPHL) Output Examples of Falling Time (TPHL) Output Part Number tPHL[µs] -40°C tPHL[µs] ,+25°C tPHL[µs],+105°C BD5227G 30.8 30 28.8 BD5327G 26.8 26 24.8 *This data is for reference only. The figures will vary with the application, so please confirm actual operating conditions before use. Explanation of Operation For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD52 □□G/FVE series uses an open drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply]. Fig.15 (BD52 □□Type Internal Block Diagram) Fig.16 (BD53 □□Type Internal Block Diagram) Timing Waveforms Example: the following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in Fig.15 and 16). 1 When the power supply is turned on, the output is unsettled from after over the operating limit voltage (VOPL) until TPHL. There fore it is possible that the reset signal is not outputted when the rise time of VDD is faster than TPHL. 2 When VDD is greater than VOPL but less than the reset release voltage (VDET+ ∆VDET), the CT terminal (VCT) and output (VOUT) voltages will switch to L. 3 If VDD exceeds the reset release voltage (VDET+ ∆VDET), then VOUT switches from L to H (with a delay to the CT terminal). 4 If VDD drops below the detection voltage (VDET) when the power supply is powered down or when there is a power supply fluctuation, VOUT switches to L (with a delay of TPHL). 5 The potential difference between the detection voltage and the release voltage is known as the hysteresis width ( ∆VDET). The system is designed such that the output does not flip-flop with power supply fluctuations within this hysteresis width, preventing malfunctions due to noise. Vref VDD GND CT R1 R2 R3 Q3 Q1 VOUT RESET RL VDD Vref VDD GND CT R1 R2 R3 Q3 Q2 VOUT RESET Q1 VDD VDD VDET+ΔVDET VDET VOPL 0V 1/2 VDD TPHL ① TPLH TPHL TPLH ② ③ ④ VCT ⑤ VOUT Fig.17 VDD-VCTH VDD |
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