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BD9756AMWV Datasheet(PDF) 3 Page - Rohm |
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BD9756AMWV Datasheet(HTML) 3 Page - Rohm |
3 / 5 page 3/4 REV. B ○Pin Assignment ・Block Diagram ○Pin Description ○Package Pin Name Description VBAT Input for battery voltage VIN Returning voltage from output terminal CPOUT Output terminal for Charge Pump GND Ground terminal C+H Terminal for connecting flying capacitor for Charge Pump(H side) C+L Terminal for connecting flying capacitor for Charge Pump(L side) PGND13,2,4,567 Ground terminal for internal FET VREGA VREGA output VREF CH5 base bias voltage PVCC5 CH5 PMOS VCC input for driver Pin Name Description OUT5 Terminal for connecting gate of CH5 PMOS Hx1,3,4 Input terminal for synchronous High side switch, Power supply for Pch Driver Lx1,3,4,6,7 Terminal for connecting inductors Hx2 Power supply for channel 2 Lx21 Terminal for connecting inductor for CH2 input Lx22 Terminal for connecting inductor for CH2 output VOUT2 CH2 output voltage HS67H Power supply for internal load switch HS6L,HS7L Output terminal for internal load switch INV1,2,3,4,6,7 Error AMP inverted input NON5 Error AMP non-inverted input Pin Name Description INV7I Error AMP inverted input RT For connecting a resistor to set the OSC frequency SCP For connecting a capacitor to set up the delay time of the SCP UDSEL4 Step-up/down switching mode selection(H: step-down, L:step-up) STB124,3,56 ON/OFF switch H: operating over 1.5V PWM7 ON/OFF switch Duty input for PWM brightness control Fig. 2 Fig. 1 PWM & LOGIC BLOCK 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1 2 3456 78 9 10 11 33 32 31 30 29 28 27 26 25 24 23 50k PRE DRIVER PRE DRIVER PRE DRIVER PRE DRIVER PRE DRIVER B.G.CTL + - REF 0V + - REF 1.0V + - REF 1.0V + - + - REF 0.8V + - REF 0.8V + - REF 0.8V + - REF 0.8V SCP OSC CHARGE PUMP 1.0V VREF 2.5V REG TSD DAC UVLO NON5 INV6 INV7 INV7I PWM7 HS6L HS67H HS7L Lx7 PGND567 Lx6 INV2 INV4 PGND4 Lx4 Hx4 Hx2 Lx21 PGND2 Lx22 VOUT2 INV3 OCP OCP OCP B D 9 7 5 6 M W LOT No. A |
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