DAC5670

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SGLS394 – MARCH 2010

Digital Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CMOS Interface (SLEEP, RESTART, INV_CLK, NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS)

High-level input voltage

2

3

V

Low-level input voltage

0

0

0.8

V

High-level input current

0.2

10

mA

Low-level input current

-10

-0.2

mA

Input capacitance

pF

Differential Data Interface (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0], DTCLK_P, DTCLK_N)

Differential input threshold

–100

100

mV

Internal termination impedance

80

100

125

Ω

Input common mode

0.6

1.4

V

Input capacitance

pF

Clock Inputs (DACCLK_P, DACCLK_N)

|DACCLK_P -

Clock differential input voltage

200

1000

mV

DACCLK_N|

Clock duty cycle

40

60

%

VCLKCM

Clock common mode

1.0

1.4

V

(1)

Typicals are characterization values at 25C and AVDD = 3.3V. These parameters are characterized but not production tested

(2)

Specified by design

Table 1. Thermal Information

Parameter

TEST CONDITIONS

TYPICAL

UNIT

Non-thermally enhanced JEDEC standard

Junction-to-free-air thermal resistance

41.3

°C/W

PCB, per JESD-51, 51-3

RqJC

Junction-to-case thermal resistance

MIL-STD-883 test method 1012

3.8

°C/W

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