Technical Note

6/12

BU1851GUW

www.rohm.com

2009.09 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

● Functional Description

1. Power mode

The device enters the state of Power Down when XRST=”Low”. When XRST=High after powered, the device enters the standby

state.

Power On Reset

A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is not used.

In this case, the XRST port must be connected to high (VDD), and the PORENB port must be connected to low (VSS). If

you don’t want to use Power On reset, you must connect PORENB port to high (VDD).

Power Down State

The device enters Power Down state by XRST=”Low”. An internal circuit is initialized, and key encoding and 3wire interface

are invalid. Power On Reset becomes inactive during this state.

Stand-by State

The device enters the stand-by state by setting XRST to "High". In this state, the device is waiting for keys pressed.

When a key is pressed, the state will change to operation. Power On Reset is active in this state if PORENB = low.

Operating State

The device enters the operating state by pressing keys. The device will scan the key matrix and encode the key code,

and then the 3wire interface tries to start communication by driving KINT “Low”. See sec.2 for the details. After

communicating with host device, when no keys are pressed, the device returns to the stand-by state. Power On

Reset is active in this state if PORENB=low.

2. 3wire Interface

KSDA

KSCL

KINT

Bit7

Bit6

Bit5

Bit0

invalid

Start bit

sent by BU1851

sent by host device

Fig.5 Protocol

Figure 5 shows the protocol of BU1851. BU1851 protocol basically consists of 3 wire configuration (KINT, KSCL, and

KSDA) as shown above. Note that this 3wire interface is completely different from I2C and other standard bus interface.

Procedure

1.

When BU1851 detects key events, KINT interrupt is generated to host with driving Low.

2.

After the host detects KINT interrupt, the host is supposed to send start bit.

3.

After BU1851 detects start bit, the 8bit data (key code) transmission on KSDA will start synchronized with the rising

edge of KSCL clock signal, which is sent from the host.

4.

8 bit data are followed by “0” (9

timeout

Fig.6 shows the 3wire timeout sequence. It is suppose to happen when Host doesn’t response anything in a certain time.

1.

bu1851 generates KINT interrupt.

2.

But Host doesn’t response within 500ms.

3.

BU1851 stops KINT, and tries to communicate again by generating KINT.

4.

BU1851 will go into the stand-by state when the communication fails five times.