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WM2618 Datasheet(PDF) 7 Page - Wolfson Microelectronics plc |
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WM2618 Datasheet(HTML) 7 Page - Wolfson Microelectronics plc |
7 / 10 page Production Data WM2618 WOLFSON MICROELECTRONICS LTD PD Rev 1.1 October 2000 7 SOFTWARE CONFIGURATION OPTIONS The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12- bit data word. D15-D12 hold the programmable options which are summarized in Table 3. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Program Bits New DAC value Table 2 Serial Word Format PROGRAM BITS D15 D14 D13 D12 DEVICE FUNCTION 1X X X Write to latch A with serial interface register data and latch B updated with buffer latch data. 0X X 0 Write to latch B and double buffer latch. 0X X 1 Write to double buffer latch only. X0 X X 12 µs settling time. X1 X X 4 µs settling time. XX 0 X Powered-up operation. XX 1 X Power down mode. Table 3 Program Bits D15 to D12 Function PROGRAMMABLE SETTLING TIME Settling time is a software selectable 12 µs or 4µs, typical to within ±0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 4 µs, a ZERO defines a settling time of 12 µs. PROGRAMMABLE POWER DOWN The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down. FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12) PURPOSE AND USE OF THE DOUBLE BUFFER Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change after a single write. This is achieved by the two following steps. • A double buffer only write is executed to store the new DAC B data without changing the DAC A and B outputs. • Following the previous step, a write to latch A is executed. This writes the serial interface register (SIR) data to latch A and also writes the double buffer contents to latch B. Thus both DACs receive their new data at the same time and so both DAC outputs begin to change at the same time. Unless a double buffer only write is issued, the latch B and double buffer contents are identical. Thus, following a write to latch A or B with another write to latch A does not change the latch B contents. Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections. LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = X) The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output updates of both DACs. |
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