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WM2631IDT Datasheet(PDF) 11 Page - Wolfson Microelectronics plc

Part # WM2631IDT
Description  Octal 10-bit, Serial Input, Voltage Output DAC with Internal Reference
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM2631IDT Datasheet(HTML) 11 Page - Wolfson Microelectronics plc

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Production Data
WM2631
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 April 2001
11
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. Bits D11 (MSB) to D2 (LSB) from these registers are
transferred to the respective DAC when the LOADB input (pin 18) is low. Bits D1 and D0 are unused
and should be set to 0. For instantaneous updating, LOADB can be held low permanently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power
Down and Data Input Format.
BIT
D11
D10
D9
D8D7D6D5
D4
D3
D2
D1
D0
Function
X
X
XXXX
X
PD
DO
R1
R0
IM
Default
X
X
XXXX
X
0
0000
Table 5 Control Register 0 Map
BIT
DESCRIPTION
0
1
PD
Full device Power Down
Normal
Power Down
DO
DOUT Enable
Disabled
Enabled
R1
Int / Ext Reference Select
External
Internal
R0
Internal Reference Select
1.024V
2.048V
IM
Input Mode
Straight Binary
Two’s Complement
X
Reserved
Table 6 Control Register 0 Functionality
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling
time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of
the device. The settling time in fast mode is typically 1
µs. In slow mode, the settling time is typically
3
µs and power consumption is reduced.
BIT
D11
D10
D9
D8D7D6D5
D4
D3
D2
D1
D0
Function
X
X
X
X
PGH
PEF
PCD
PAB
SGH
SEF
SCD
SAB
Default
X
X
X
X
0
0
0
0
0
0
0
0
Table 7 Control Register 1 Map
BIT
DESCRIPTION
0
1
PXY
Power Down DACs X and Y
Normal
Power Down
SXY
Speed Setting for DACs X and Y
Slow
Fast
Table 8 Control Register 1 Functionality
DAC PRESET REGISTER
The Preset register (address 10) makes it possible to update all eight DACs at the same time. The
value stored in this register becomes the digital input to all the DACs when the asynchronous PREB
input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are
set to zero scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing
data to one DAC will automatically write the complement to the other DAC in the pair. For example,
writing a value of 1023 to address 12 will set DAC A to full scale and DAC B to zero scale.


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