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WM2639CDT Datasheet(PDF) 5 Page - Wolfson Microelectronics plc |
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WM2639CDT Datasheet(HTML) 5 Page - Wolfson Microelectronics plc |
5 / 10 page Production Data WM2639 WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 July 1999 5 Test Conditions: RL = 10k Ω, C L = 100pF. VDD = 5V ±± 10%, V REF = 2.048V and VDD = 3V ±± 10%, V REF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Signal to noise ratio SNR fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25 °C See Note 12 73 78 dB Signal to noise and distortion ratio SNRD fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25 °C See Note 12 61 67 dB Total harmonic distortion THD fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA=25 °C See Note 12 -69 -62 dB Spurious free dynamic range SPFDR fs = 480ksps, fOUT = 1kHz, BW = 20kHz, TA = 25 °C See Note 12 63 74 dB Reference configured as input Reference input resistance RREFIN 10 M Ω Reference input capacitance CREFIN 55 pF Reference feedthrough VREF = 1VPP at 1kHz + 1.024Vdc, DAC code 0 -60 dB Reference input bandwidth VREF= 0.2VPP + 1.024V d.c. DAC code 2048 Slow Fast 500 900 kHz kHz Reference configured as output Low reference voltage VREFOUTL 1.003 1.024 1.045 V High reference voltage VREFOUTH VDD > 4.75V 2.027 2.048 2.069 V Output source current IREFSRC 1 mA Output sink current IREFSNK -1 mA Load Capacitance 100 pF PSRR -48 dB Digital Inputs High level input current IIH Input voltage = VDD 1 µA Low level input current IIL Input voltage = 0V -1 µA Input capacitance CI 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k Ω load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10k Ω load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. |
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