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WM8148 Datasheet(PDF) 7 Page - Wolfson Microelectronics plc |
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WM8148 Datasheet(HTML) 7 Page - Wolfson Microelectronics plc |
7 / 43 page WM8148 Production Data WOLFSON MICROELECTRONICS LTD PD Rev 4.0 April 1999 7 INPUT VIDEO SAMPLING (EXTERNAL VSMP) MCLK VSMP INPUT VIDEO t PER t VSMPSU t VSMPH t VSU t VH t RSU t RH Figure 1 Input Video Timing (External VSMP) TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period (dependent on mode selected) tPER 20.8 ns MCLK duty cycle 45 55 % VSMP set-up time tVSMPSU 2ns VSMP hold time tVSMPH 5ns Video level set-up time tVSU 10 ns Video level hold time tVH 10 ns Reset level set-up time tRSU 10 ns Reset level hold time tRH 10 ns Notes: 1. tVSU and tRSU denote the set-up time required from when the input video signal has settled. 2. The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of control bits RESREF[3:0]. 3. Parameters are measured at 50% of the rising/falling edge. |
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