Production Data

WM8720

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 November 2000

11

SOFTWARE CONTROL INTERFACE

The WM8720 can be controlled using a 3-wire serial interface. MD/DM (pin 6) is used for the program

data, MC/IWL (pin 5) is used to clock in the program data and ML/I2S (pin 4) is use to latch in the

program data. The 3-wire interface protocol is shown in Figure 7.

ML/I2S

MC/IWL

MD/DM

D15

D6

D7

D8

D9

D10

D11

D12

D13

D14

D1

D2

D3

D4

D5

D0

Figure 7 3-Wire Serial Interface

REGISTER MAP

WM8720 controls the special functions using 4 program registers, which are 16-bits long. These

registers are all loaded through input pin MD/DM. After the 16 data bits are clocked in, ML/I2S/IWL is

used to latch in the data to the appropriate register. Table 7 shows the complete mapping of the

4 registers.

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

M0

--

----

A1

A0

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

M1

-----

A1

A0

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

M2

-----

A1

A0

PL3

PL2

PL1

PL0

IW1

IW0

OPE

DE

MU

M3

-----

A1

A0

IZD

SF1

SF0

---

ATC

LRP

I

Table 7 Mapping of Program Registers

REGISTER NAME

BIT NAME

DEFAULT

DESCRIPTION

Register 0 (M0)

A[1:0] = 00

AL[7:0]

LDL

1111 1111

0

DAC attenuation data for left channel

Attenuation data load control for left channel

Register 1 (M1)

A[1:0] = 01

AR[7:0]

LDR

1111 1111

0

DAC attenuation data for right channel

Attenuation data load control for right channel

Register 2 (M2)

A[1:0] = 10

MU

DE

OPE

IW[1:0]

PL[3:0]

0

0

0

00

1001

Left and right DACs soft mute control

De-emphasis control

Left and right DACs operation control

Input audio word resolution

DAC output control

Register 3 (M3)

A[1:0] = 11

I

LRP

ATC

SF[1:0]

IZD

0

0

0

00

0

Audio data format select

Polarity of LRCIN (pin 7) select

Attenuator control

Sampling rate select

Infinite zero detection circuit control and automute control

Table 8 Internal Register Mapping

DAC OUTPUT ATTENUATION

Register 0 (A[1:0] = 00) is used to control left channel attenuation. Bits 0-7 (AL[7:0]) are used to

determine the attenuation level Table 9. The level of attenuation is given by: