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SG32825CQ Datasheet(PDF) 6 Page - Microsemi Corporation |
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SG32825CQ Datasheet(HTML) 6 Page - Microsemi Corporation |
6 / 7 page H IGH -S PEED C URRENT -M ODE PWM SG1825C/SG2825C/SG3825C PRODUCT DA T ABOOK 1996/1997 Copyright © 1994 Rev. 1.3a 6 N OT R ECOMMENDED FOR N EW D ESIGNS APPLICATION INFORMATION The SG1825C, like all high-speed circuits, requires extra attention to external conductor and component layout to minimize undesired inductive and capacitive effects. All lead lengths must be as short as possible. The best printed circuit board choice would be a four-layer design, with the two internal planes supplying power and ground. Signal interconnects should be placed on the outside, giving a conductor-over-ground-plane (microstrip) configuration. A two-sided printed circuit board with one side dedicated as a ground plane is next best, and requires careful component placement by a skilled pc designer. Two supply bypass capacitors should be employed: a low-inductance 0.1µF ceramic within 0.25 inches of the +V IN pin for high frequencies, and a 1 to 5µF solid tantalum within 0.5 inches of the V C pin to provide an energy reservoir for the high-peak output currents. A low-inductance .01µF bypass for the reference output is also recommended. HIGH-SPEED LAYOUT AND BYPASSING FIGURE 1. HIGH-SPEED LAYOUT and BYPASSING FREQUENCY SYNCHRONIZATION Two or three SG1825C oscillators may be locked together with the interconnection scheme shown, if the devices are within an inch or so of each other. A master unit is programmed for desired frequency with R T and C T as usual. The oscillators in the slave units are disabled by grounding CT and by connecting R T to VREF. The logic in the slave units is locked to the clock of the master with the wire-OR connection shown. Many SG1825Cs can be locked to a master system clock by wiring the oscillators as slave units, and distributing the master clock to each using a tree-fanout geometry. Since the SG1825C typically draws 700µA of supply current before turning on, a low power bleeder resistor from the rectified AC line supply is all that is required for startup. A start capacitor, C S, is charged with the excess current from the bleeder resistor. When the turn-on threshold voltage is reached, the PWM circuit becomes active, energizing the power transistors. The additional operating current required by the PWM is then provided by a bootstrap winding on the main high-frequency power transformer. SOFTSTART CIRCUIT / OUTPUT DUTY CYCLE LIMIT The softstart pin of the SG1825C is held low when either the chip is in the micropower mode, or when a voltage greater than +1.4 volts is present at the I LIM/S.D. pin. The maximum positive swing of the voltage error amplifier is clamped to the Softstart pin voltage, providing a ramp-up of peak charging currents in the power semiconductors at turn-on. In some cases, the duration of the Shutdown signal can be too short to fully discharge the softstart capacitor. The illustrated resistor/discrete PNP transistor configuration can be used to shorten the discharge time by a factor of 50 or more. When the internal discharge transistor in the SG1825C turns on, current will flow through surge limit resistor R1. As the resistor drop approaches 0.6 volts, the external PNP turns on, providing a low resistance discharge path for the energy in the softstart capacitor. The capacitor will be rapidly discharged to +0.7 volts, which corresponds to zero duty cycle in the pulse width modulator. APPLICATION FIGURES FIGURE 3. SOFTSTART FAST RESET MICROPOWER STARTUP 13 12 10 V C POWER GND GND 15 +V IN 0.1µF + V IN R B C S TO POWER TRANSFORMER SG1825C L1 GND L2 1µF C T R T 10 12 6 PWR GND GND +V IN 15 0.1µF + V IN 5 SG1825C CLK 4 C T R T 10 12 6 PWR GND GND +V IN 15 0.1µF 5 SG1825C V REF 16 CLK 4 C T R T MASTER SLAVE V REF V C 0.01µF V REF 10 12 13 PWR GND GND +V IN 15 0.1µF +V IN 1µF 16 SG1825C FIGURE 2. MICROPOWER STARTUP V C C SS 10 12 13 PWR GND GND +V IN 15 0.1µF + V IN 1µF 8 SG1825C R 1 100 W C SOFTSTART FIGURE 4. OSCILLATOR SYCHRONIZATION |
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