BD8132FV, BD8139AEFV

Technical Note

9/20

www.rohm.com

2009.07 - Rev.B

© 2009 ROHM Co., Ltd. All rights reserved.

[BD8132FV]

●

Serial communications

The serial data control block consists of a register that stores data from the LATCH, CLK, and SDIN pins, and a DAC circuit

that receives the output from this register and provides adjusted voltages to other IC blocks.

When the IC's power supply is activated, the reset function operates to set the register to a preset value. The first bit is for

testing use only and should always be set to 0. The next bit is used to select the OSC mode. Inputting a value of 0 selects

internal frequency mode and uses a frequency of 80 kHz. Entering a value of 1 selects external frequency mode. Input an

external clock signal from the OSC pin.

Fig. 21 Serial Block Diagram

(1) Serial communications timing

The 17-bit serial data input from the SDIN pin is read into the shift register using the rising edge of the signal input to the

CLK pin. This data is then loaded to the DAC register using the rising edge of the signal input to the LATCH pin.

If the data loaded into the shift register while the LATCH pin is low consists of less than 17 bits, the loaded data is

discarded. If the data exceeds 17 bits, the last 17 bits to be loaded are treated as valid.

(2) Serial data

The following table illustrates the format of serial data input to the SDIN pin.

First →

→Last

d0

d1

d2

d3

d4

d5

d6

d7

d8

d9

d10

d11

d12

d13

d14

d15

d16

0

X

Register address

Data

Register

Address

Behavior when data increases

Preset value

d2

d3

d4

d5

d6

d7

to

d16

Register 0

0

0

0

0

0

V0 voltage value increases

00000

00000

Register 1

0

0

0

0

1

V1 voltage value increases

00000

00000

Register 2

0

0

0

1

0

V2 voltage value increases

00000

00000

Register 3

0

0

0

1

1

V3 voltage value increases

00000

00000

Register 4

0

0

1

0

0

V4 voltage value increases

00000

00000

Register 5

0

0

1

0

1

V5 voltage value increases

00000

00000

Register 6

0

0

1

1

0

V6 voltage value increases

00000

00000

Register 7

0

0

1

1

1

V7 voltage value increases

00000

00000

Register 8

0

1

0

0

0

V8 voltage value increases

00000

00000

Register 9

0

1

0

0

1

V9 voltage value increases

00000

00000

Register A

0

1

0

1

0

VA voltage value increases

00000

00000

Register B

0

1

0

1

1

VB voltage value increases

00000

00000

Register C

0

1

1

0

0

VC voltage value increases

00000

00000

Register D

0

1

1

0

1

VD voltage value increases

00000

00000

Register E

0

1

1

1

0

VE voltage value increases

00000

00000

Register F

0

1

1

1

1

VF voltage value increases

00000

00000

Register G

1

0

0

0

0

VG voltage value increases

00000

00000

Register H

1

0

0

0

1

VH voltage value increases

00000

00000

Register I

1

0

0

1

0

Vcom voltage value increases

00000

00000

Shift register

OUT0 to OUTI

registers

DAC

Address

decoder

Serial data control block diagram

Clock control

LATCH

CLK

SDIN

10 bits

5 bits

Test

mode

1 bit

OSC

mode

1 bit

Serial communications timing

LATCH

CLK

SDIN

Fig. 22 Serial Communications Timing Chart