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X24012S-3 Datasheet(PDF) 1 Page - Xicor Inc. |
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X24012S-3 Datasheet(HTML) 1 Page - Xicor Inc. |
1 / 14 page X24012 1 START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC DOUT ACK E2PROM 32 X 32 DATA REGISTER START CYCLE (8) VCC R/W PIN (4) VSS (5) SDA (6) SCL (3) A2 (2) A1 (1) A0 DOUT LOAD INC CK 8 DESCRIPTION The X24012 is a CMOS 1024 bit serial E2PROM, internally organized as one 128 x 8 bank. The X24012 features a serial interface and software protocol allow- ing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus. Xicor E2PROMs are designed and tested for applica- tions requiring extended endurance. Inherent data re- tention is greater than 100 years. The X24012 is avail- able in eight pin DIP and SOIC packages. FEATURES • 2.7 to 5.5V Power Supply • Low Power CMOS —Active Current Less Than 1 mA —Standby Current Less Than 50 µA • Internally Organized 128 x 8 • Self Timed Write Cycle —Typical Write Cycle Time of 5 ms • 2 Wire Serial Interface —Bidirectional Data Transfer Protocol • Four Byte Page Write Operation —Minimizes Total Write Time Per Byte • High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years © Xicor, 1991 Patents Pending Characteristics subject to change without notice 1K X24012 128 x 8 Bit Serial E2PROM FUNCTIONAL DIAGRAM 3847 FHD F01 Preliminary Information Pin 7 No Connect 3847-1 |
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