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X24165S-2.7 Datasheet(PDF) 10 Page - Xicor Inc. |
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X24165S-2.7 Datasheet(HTML) 10 Page - Xicor Inc. |
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10 / 17 page  X24165 10 Block Protect Bits The Block Protect Bits BP0 and BP1 determine which blocks of the memory are write-protected: Programmable Hardware Write Protect The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Write Protect Register control the programmable hardware write protect feature. Hardware write protection is enabled when the WP pin and the WPEN bit are both HIGH, and disabled when either the WP pin is LOW or the WPEN bit is LOW. When the chip is hardware write-protected, nonvolatile writes are disabled to the Write Protect Register, including the BP bits and the WPEN bit itself, as well as to block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. Note that since the WPEN bit is write-protected, it cannot be changed back to a LOW state, and write protection is disabled as long as the the WP pin is held HIGH. Table 2 defines the write protection status for each state of WPEN and WP. Table 1. Block Protect Bits 6551 FRM T02 BP1 BP0 Protected Addresses 0 0 None 0 1 600h–7FFh Upper 1/4 1 0 400h–7FFh Upper 1/2 1 1 0000h–7FFh Full Array (WPR not included) Table 2. Write Protect Status Table 6551 FRM T03 WP WPEN Memory Array (Not Block Protected) Memory Array (Block Protected) BP Bits WPEN Bit 0 X Writable Protected Writable Writable X 0 Writable Protected Writable Writable 1 1 Writable Protected Protected Protected |
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