X24C00

7

Bus Timing

tSU:STA

tHD:STA

tHD:DAT

tSU:DAT

tLOW

tSU:STO

tR

tBUF

SCL

SDA IN

SDA OUT

tDH

tAA

tF

tHIGH

3836 FHD F10

WRITE CYCLE LIMITS

Symbol

Parameter

Min.

Max.

Units

Write Cycle Time

5

ms

3836 PGM T09

Write Cycle Timing

3836 ILL F11.1

SDA

tWR

SCL

D0

START

CONDTION

X24C00

ADDRESS

Note:

(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the

write cycle, the X24C00 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start

conditions.