X24C45

3

DEVICE OPERATION

The X24C45 contains an 8-bit instruction register. It is

accessed via the DI input, with data being clocked in on

the rising edge of SK. CE must be HIGH during the entire

data transfer operation.

Table 1. contains a list of the instructions and their

operation codes. The most significant bit (MSB) of all

instructions is a logic one (HIGH), bits 6 through 3 are

either RAM address bits (A) or don’t cares (X) and bits

2 through 0 are the operation codes. The X24C45

requires the instruction to be shifted in with the MSB first.

After CE is HIGH, the X24C45 will not begin to interpret

the data stream until a logic “1” has been shifted in on DI.

Therefore, CE may be brought HIGH with SK running

and DI LOW. DI must then go HIGH to indicate the start

condition of an instruction before the X24C45 will begin

any action.

In addition, the SK clock is totally static. The user can

completely stop the clock and data shifting will be

stopped. Restarting the clock will resume shifting of

data.

RCL and

RECALL

Either a software RCL instruction or a LOW on the

into RAM. This software or hardware recall operation

sets an internal “previous recall” latch. This latch is reset

upon power-up and must be intentionally set by the user

to enable any write or store operations. Although a recall

operation is performed upon power-up, the previous

recall latch is not set by this operation.

WRDS and WREN

Internally the X24C45 contains a “write enable” latch. This

latch must be set for either writes to the RAM or store

the latch and the WRDS instruction resets the latch,

tively protecting the nonvolatile data from corruption. The

write enable latch is automatically reset on power-up.

STO

The software STO instruction will initiate a transfer of

against unwanted store operations, the following condi-

tions must be true:

• STO instruction issued.

• The internal “write enable” latch must be set

(WREN instruction issued).

• The “previous recall” latch must be set (either a

software or hardware recall operation).

Once the store cycle is initiated, all other device func-

tions are inhibited. Upon completion of the store cycle,

the write enable latch is reset. Refer to Figure 4 for a

state diagram description of enabling/disabling condi-

tions for store operations.

TABLE 1. INSTRUCTION SET

Instruction

Operation

WRDS (Figure 3)

1XXXX000

Reset Write Enable Latch (Disables Writes and Stores)

STO (Figure 3)

1XXXX001

ENAS

1XXXX010

Enable AUTOSTORE Feature

WRITE (Figure 2)

1AAAA011

Write Data into RAM Address AAAA

WREN (Figure 3)

1XXXX100

Set Write Enable Latch (Enables Writes and Stores)

RCL (Figure 3)

1XXXX101

READ (Figure 1)

1AAAA11X

Read Data from RAM Address AAAA

3833 PGM T11

X = Don’t Care

A = Address