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X68C75L Datasheet(PDF) 10 Page - Xicor Inc. |
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X68C75L Datasheet(HTML) 10 Page - Xicor Inc. |
10 / 26 page 10 X68C75 SLIC® E2 Configuration Register (CR) The Configuration Register is a volatile register used to configure the operation of the I/O ports. The configura- tion register allows the microcontroller to designate whether each of the two ports is an input or output, what type of output drive is to be used, and specifies the polarity of the two strobe lines, STRA and STRB. The bit map of configuration register is shown below. The IRST bit in the configuration register controls the method used to clear the port interrupt request flags (INTA, INTB). The interrupts are reset by either reading the interrupt source or writing to the interrupt status register. The interrupt must be disabled prior to chang- ing strobe polarity bits (STPA, STPB), or port direction bits (DIRA, DIRB) in CR. Otherwise, any attempt to modify the status of these bits may cause an interrupt to occur. Port Data Registers (PDR) The PDRA/PDRB are byte-wide latches which hold port data. When a port is configured as an output, the outputs of its PDR latch are connected to the port pins. Writing to PDR generates a pulse on the port strobe pin and latches the data. If a port is configured as an input, the inputs of its PDR latch are connected to the port pins. External data is latched into PDR on the positive edge of its clock. The port strobe input and strobe polarity bit (STPA, STPB) are XORed to generate the PDR input clock. Port Pin Registers (PPR) The read-only Port Pin Registers are used for reading the current status of the external I/O port pins. Accessing the PPR causes the values on the port pins to be placed on the data bus. The port direction control bits in configuration register set the direction for the entire port and no control mechanism is provided to program the direction of individual pins. However, the ports have a flexible archi- tecture which allows operating I/O ports in bidirectional mode using the PPR read feature. A port can be operated in input/output mode by config- uring it as an open-drain output port. The port wire-OR bit (AWO, or BW) and its port data direction bit (DIRA, or DIRB) in CR, should be set to “1”. The PDR bits which correspond to the port pins assigned as inputs should be programmed to “1”. For monitoring the status of the input pins, the PPR can be read. In this application the port strobe pin and the PDR latch are in output mode. In open-drain mode, there are weak internal pull-ups on the port pins, however external pull-ups must be used for proper switching of the I/O lines. Static RAM Block There are 16 bytes of volatile static RAM registers mapped to the SFR region. They reside in the 200H- 20FH area offset from the SFR base address. Accessing these registers has to be done through external RAM operations for both writes and reads. Figure 11. Configuration Register IRST 2899 ILL F13.1 1 AWO BWO DIRA DIRB STPA STPB 76543210 Interrupt Request Reset Mode This bit controls the clearing of the interrupt request flag. “0” = Reading the interrupt source “1” = Writing to the request register Port A – Outputs “0” = CMOS “1” = Open-Drain Port B – Outputs “0” = CMOS “1” = Open-Drain Port A – Direction Flag “0” = Input mode “1” = Output mode Port B – Direction Flag “0” = Input mode “1” = Output mode Strobe B – Strobe Pin Polarity “0” = Active LOW “1” = Active HIGH Strobe A – Strobe Pin Polarity “0” = Active LOW “1” = Active HIGH |
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