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X88C75LM Datasheet(PDF) 8 Page - Xicor Inc. |
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X88C75LM Datasheet(HTML) 8 Page - Xicor Inc. |
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8 / 27 page  X88C75 SLIC® E2 8 Figure 8. Setting the SFR Map Register Figure 9. Setting Program Memory Map Register BITS 7:6 Setting these two bits to any combination other than “00” or “11” will interfere with device proper operation. E2 Memory Map Register (EEM) Default = 08 0 0 LAM 0 RST A15 A14 A13 76 2887 ILL F11 543 21 0 A15-A13 Modifying these three bits changes the location of the program memory within the address map.The A15-A13 correspond to the upper three address bits of the 8K- byte page where program memory will be mapped. RST The RST bit controls the polarity of the RESET input pin. “0” = RESET is Active LOW “1” = RESET is Active HIGH LAM Port B can be configured as either a general purpose I/O port (normal I/O mode), or latched address mode (LAM). The LAM option programs port B to output the demultiplexed low order byte of the address latched into the X88C75 by ALE. The LAM bit selects between these two modes. “0” = PORT B is I/O Port “1” = Port B outputs low address byte (A7-A0) Setting the Mapping Registers The mapping registers are written using a modified version of the Software Data Protection sequence. All timings must adhere to the normal Software Data Pro- tection sequence. The complemented contents of the SFR map register and the E2 memory map register can be read by the microcontroller at their corresponding SFR addresses. The physical memory location of these registers can be derived by adding the following offset to the SFR base address: SFR Map Register 00H E2 Memory Map Register 38H If the regions specified in the map registers overlap, only the SFR will be accessible. AA b2 P 555 b1 b0 55 b2 AAA AAA b1 b0 A0 b2 P 555 b1 b0 AA b2 P 555 b1 b0 D0 Delay of tWC Exit Routine b2 P 2887 ILL F12.1 b1 b0 XXX Desired Value b2 P b1 b0 X = Don’t Care B[2:0] = E2M [2:0] P = Address bit (A12) of the memory plane not being read. P AA b2 P 555 b1 b0 55 b2 AAA AAA b1 b0 A0 b2 P 555 b1 b0 AA b2 P 555 b1 b0 E0 b2 P 2887 ILL F13.1 b1 b0 XXX Desired Value b2 P b1 b0 P Delay of tWC Exit Routine X = Don’t Care B[2:0] = E2M [2:0] P = Address bit (A12) of the memory plane not being read. |
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