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X25648V14-2.7 Datasheet(PDF) 5 Page - Xicor Inc. |
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X25648V14-2.7 Datasheet(HTML) 5 Page - Xicor Inc. |
5 / 16 page X25648/49, X25328/29, X25168/69 5 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16 BIT ADDRESS 15 14 13 3 2 1 0 7036 FRM 03 While the write is in progress following a Status Register or E2PROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. RESET/RESET Operation The RESET (X25XX3) output is designed to go LOW whenever VCC has dropped below the minimum trip point, Vtrip. The RESET (X25XX5) output is designed to go HIGH whenever VCC has dropped below the minimum trip point, Vtrip. The RESET/RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The Write Enable Latch is reset. • The Flag Bit is reset. • Reset Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inad- vertent writes: • A WREN instruction must be issued to set the Write Enable Latch. • CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. Figure 1. Read E2PROM Array Sequence |
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