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XM28C020PM-12 Datasheet(PDF) 3 Page - Xicor Inc. |
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XM28C020PM-12 Datasheet(HTML) 3 Page - Xicor Inc. |
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3 / 16 page  XM28C020 3 DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture elimi- nates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The XM28C020 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, which- ever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms (see Note 4). Page Write Operation The page write feature of the XM28C020 allows the entire memory to be written in 10 seconds. Page write allows two to 128 bytes of data to be consecutively written to the XM28C020 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A17) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to 127 bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 µs. Write Operation Status Bits The XM28C020 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment 5 TB DP 43210 I/O RESERVED TOGGLE BIT DATA POLLING 3872 FHD F09 DATA Polling (I/O7) The XM28C020 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the XM28C020, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the XM28C020 is in the protected state and an illegal write operation is attempted, DATA Polling will not operate. Toggle Bit (I/O6) The XM28C020 also provides another method for deter- mining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from “1” to “0” and “0” to “1” on subsequent attempts to read the last byte written. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. |
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