AD9553 datasheet(4/44 Pages) AD

Part #	AD9553

Description	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

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Manufacturer	AD [Analog Devices]

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AD9553

Rev. 0 | Page 4 of 44

RESET PIN

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS1

Input Voltage High, VIH

1.96

V

Input Voltage Low, VIL

0.85

V

Input Current High, IINH

0.3

12.5

μA

Input Current Low, IINL

31

43

μA

MINIMUM PULSE WIDTH LOW

150

μs

Tested with an active source driving the RESET pin.

1 The RESET pin has a 100 kΩ internal pull-up resistor.

REFERENCE CLOCK INPUT CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL INPUT

Input Frequency Range

0.008

250

MHz

710

MHz

Assumes minimum LVDS input level and requires

bypassing of the /5 divider and 2× multiplier.

Common-Mode Internally Generated

Input Voltage

613

692

769

mV

Use ac coupling to preserve the internal dc bias of the

differential input.

Differential Input Voltage Sensitivity

250

mV p-p

Capacitive coupling required; can accommodate single-

ended input by ac grounding unused input; the

instantaneous voltage on either pin must not exceed the

3.3 V dc supply rails.

Differential Input Resistance

5

kΩ

Differential Input Capacitance

3

pF

Duty Cycle

Pulse width high and pulse width low establish the

bounds for duty cycle.

Pulse Width Low

1.6

ns

Up to 250 MHz.

Pulse Width High

1.6

ns

Up to 250 MHz.

Pulse Width Low

0.64

ns

Beyond 250 MHz, up to 710 MHz.

Pulse Width High

0.64

ns

Beyond 250 MHz, up to 710 MHz.

CMOS SINGLE-ENDED INPUT

Input Frequency Range

0.008

200

MHz

Input High Voltage1

1.05

V

Input Low Voltage1

0.98

V

Input High Current

0.04

μA

Input Low Current

0.03

μA

Input Capacitance

3

pF

Duty Cycle

Pulse width high and pulse width low establish the

bounds for duty cycle.

Pulse Width Low

2

ns

Pulse Width High

2

ns

2× FREQUENCY MULTIPLIER

125

MHz

To avoid excessive reference spurs, the 2× multiplier

requires 48% to 52% duty cycle. Reference clock input

frequencies greater than 125 MHz require the use of the

/5 divider.

1The single-ended CMOS input is 3.3 V compatible. In the case of ac-coupling, the user must bias the input at 1.0 V dc.

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