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AD9148BBPZRL Datasheet(PDF) 5 Page - Analog Devices |
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AD9148BBPZRL Datasheet(HTML) 5 Page - Analog Devices |
5 / 73 page Preliminary Technical Data AD9148 Rev. PrA | Page 5 of 73 INPUT/OUTPUT SIGNAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CSB, RESETE, TMS, TDI, TCK) Input VIN Logic High (IOVDD = 1.8 V) 1.2 V Input VIN Logic High (IOVDD = 3.3 V) 2.0 V Input VIN Logic Low (IOVDD = 1.8 V) 0.6 V Input VIN Logic Low (IOVDD = 3.3 V) 0.8 V CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQE, PLL_LOCK, TDO) Output VOUT Logic High (IOVDD = 1.8 V) 1.4 V Output VOUT Logic High (IOVDD = 3.3 V) 2.4 V Output VOUT Logic Low (IOVDD = 1.8 V) 0.4 V Output VOUT Logic Low (IOVDD = 3.3 V) 0.4 V LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x, FRAMEA_x, FRAMEB_x) Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate, fINTERFACE (See Table 4) 1200 MSPS DAC CLOCK INPUT (CLK_P, CLK_N) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 1000 MSPS REFERENCE CLOCK INPUT (REFCLK_P/SYNC_P AND REFCLK_N/SYNC_N) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 500 MSPS Minimum Clock Rate (PLL Enabled) Loop Divider = /2 125 MSPS Loop Divider = /4 62.5 MSPS Loop Divider = /8 31.25 MSPS Loop Divider = /16 15.625 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (tPWH) 12.5 ns Minimum Pulse Width Low (tPWL) 12.5 ns Set-Up Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 23 ns Setup time, CSB to SCLK (tDCSB) 1.4 ns |
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