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DS12887+ Datasheet(PDF) 9 Page - Maxim Integrated Products |
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DS12887+ Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 22 page Pin Description (continued) PIN SO, PDIP EDIP PLCC TQFP NAME FUNCTION 22 2, 3, 16, 20, 21, 22 1, 11, 13, 18, 26 4, 6, 10, 15, 20, 23, 25, 27, 32 N.C. No Connection. This pin should remain unconnected. Pin 21 is RCLR for the DS12887A/DS12C887A. On the EDIP, these pins are missing by design. 17 17 21 18 DS Data Strobe or Read Input. The DS pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode, DS is a positive pulse during the latter portion of the bus cycle and is called data strobe. During read cycles, DS signifies the time that the device is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the device to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. DS identifies the time period when the device drives the bus with read data. In this mode, the DS pin operates in a similar fashion as the output- enable (OE) signal on a generic RAM. 18 18 22 19 RESET Active-Low Reset Input. The RESET pin has no effect on the clock, calendar, or RAM. On power-up, the RESET pin can be held low for a time to allow the power supply to stabilize. The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power-up, the time RESET is low should exceed 200ms to ensure that the internal timer that controls the device on power- up has timed out. When RESET is low and VCC is above VPF, the following occurs: A. Periodic interrupt-enable (PIE) bit is cleared to 0. B. Alarm interrupt-enable (AIE) bit is cleared to 0. C. Update-ended interrupt-enable (UIE) bit is cleared to 0. D. Periodic-interrupt flag (PF) bit is cleared to 0. E. Alarm-interrupt flag (AF) bit is cleared to 0. F. Update-ended interrupt flag (UF) bit is cleared to 0. G. Interrupt-request status flag (IRQF) bit is cleared to 0. H. IRQ pin is in the high-impedance state. I. The device is not accessible until RESET is returned high. J. Square-wave output-enable (SQWE) bit is cleared to 0. In a typical application, RESET can be connected to VCC. This connection allows the device to go in and out of power fail without affecting any of the control registers. Real-Time Clocks _____________________________________________________________________ 9 |
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