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74AUP1G19GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G19GM Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74AUP1G19_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 August 2008 3 of 17 NXP Semiconductors 74AUP1G19 Low-power 1-of-2 decoder/demultiplexer 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 74AUP1G19 A1Y GND E2Y 001aai072 1 2 3 6 VCC 5 4 74AUP1G19 GND 001aai073 A E VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 74AUP1G19 GND 001aai074 A E VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) E 3 enable input (active LOW) 2Y 4 data output (complement) VCC 5 supply voltage 1Y 6 data output (true) Table 4. Function table[1] Input Output E A 1Y 2Y LLLH L HHL HL HH HHHH |
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