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74AUP1T34GF Datasheet(PDF) 2 Page - NXP Semiconductors |
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74AUP1T34GF Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 19 page 74AUP1T34_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 4 December 2006 2 of 19 NXP Semiconductors 74AUP1T34 Low-power dual supply translating buffer 3. Ordering information 4. Marking 5. Functional diagram 6. Pinning information 6.1 Pinning Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T34GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1T34GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1T34GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 Table 2. Marking Type number Marking code 74AUP1T34GW pQ 74AUP1T34GM pQ 74AUP1T34GF pQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 001aac538 2A 4 Y 001aac537 24 001aac536 Y A Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1T34 VCC(A) VCC(Y) A GND Y 001aad741 1 2 3 5 4 74AUP1T34 A 001aad740 VCC(A) GND n.c. VCC(Y) Y Transparent top view 2 3 1 5 4 6 74AUP1T34 A 001aad832 VCC(A) GND n.c. VCC(Y) Y Transparent top view 2 3 1 5 4 6 |
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