TMC332 DATA SHEET (V. 2.04 / November 9, 2009)

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Copyright © 2009 TRINAMIC Motion Control GmbH & Co. KG

5

Pinning

A single package variant (BGA FG144, 0.5mm pitch) is available for the TMC332. For proper

operation, it is strongly recommended to connect all power and ground pins (3.3V, 1.5V, GND).

Pin

FG144

I/O

Description

NRST

F1

I

low active reset input

CLK

G1

I

clock input

nEN

H2

I

low active enable input, nEN='1' disables all gate control signals equivalent to OVC

nSCS

M3

I

low active SPI chip select input of the TMC332 driven from µC

nSCS_428

L4

I

low active SPI chip select input driven from µC to select the TMC428

SCK

M4

I

serial data clock input driven from µC

SDI

M5

I

serial data input driven from µC

SDO_OF_428

L6

I

input driven by the SDO_C of the TMC428

SDO

M6

O /

Z

serial data output to µC (from TMC332 or TMC428, depending on nSCS /

nSCS_428)

STP

J1

I

step pulse input (logical ored with internal STEP pulse via TMC428 SPI driver

chain)

DIR

K1

I

direction input (logical ored with internal STEP pulse via TMC428 SPI driver chain)

nSCS_DRV

M8

I

low active SPI chip select input driven from TMC428 (driver by nSCS_S)

SCK_DRV

L8

I

serial data clock input driven from TMC428 (driven by SCK_S)

SDI_DRV

M7

I

serial data input driven from TMC428 (driven by SDO_S)

SDO_DRV

L7

O

serial data output to TMC428 SDI_S or to next SPI driver within chain (SDI)

PH

A4

I

gate control high side, 0 : low active gate control / 1 : high active gate control

PL

B4

I

gate control low side, 0 : low active gate control / 1 : high active gate control

OVC_PH

K12

I

high side gate control outputs T1H, T2H, T3H, T4H on OVC condition

OVC_PL

K11

I

low side gate control outputs T1L, T2L, T3L, T4L on OVC condition

OVC_DISABLE

J11

I

high active OVC input (from comparator output that is high on OVC condition)

OVC_NDISABLE

J12

I

low active OVC input (from comparator output that is low on OVC condition)

OVC

H11

O

over current status ( 0 : no over current condition / 1 : over current condition)

SHAFT

A3

I

direction of motion clockwise / counter clockwise, direction depends on motor

nXY_UVW

B3

I

'0' : selects two phase stepper scheme

'1' : selects three phase stepper scheme

T1H

A5

O

T1H_Y2

Y2

deactivated (level depending on PL)

T1L

B5

O

T1L_Y2

deactivated (level depending on PH)

T2H

B6

O

T2H_Y1

Y1

T3H_W

W

T2L

C6

O

T2L_Y1

T3L_W

T3H

A7

O

T3H_X2

X2

T2H_V

V

T3L

B7

O

T3L_X2

T2L_V

T4H

B8

O

T4H_X1

X1

T1H_U

U

T4L

A9

O

T4L_X1

T1L_U

ENC_A

C1

I

3.3V input for incremental encoder signal A (a pull up-resistor might be required)

ENC_B

D1

I

3.3V input for incremental encoder signal B (a pull up-resistor might be required)

ENC_N

D2

I

3.3V input for incremental encoder signal N (a pull up-resistor might be required)

ENC_O_1

M2

O

Encoder compare output 1

ENC_O _2

L3

O

Encoder compare output 2

ENC_O _3

K4

O

Encoder compare output 3

RRC

A11

O

RC control for current measurement

COMP_ADC

B10

O

RC control for current measurement/limiting

COMP_PWM

A10

O

RC control for current limiting

CMP1P

C11

I

Positive comparator input for phase Y2

CMP1N

C12

I

Negative comparator input for phase Y2

CMP2P

D11

I

Positive comparator input for phase W/Y1

CMP2N

D12

I

Negative comparator input for phase W/Y1

CMP3P

E11

I

Positive comparator input for phase V/X2

CMP3N

E12

I

Negative comparator input for phase V/X2

CMP4P

F11

I

Positive comparator input for phase U/X1

CMP4N

F12

I

Negative comparator input for phase U/X1

STDBY

F3

I

Standby current enable (power down mode)

STANDALONE_EN

H6

I

Enable standalone mode (settings via SC_* inputs)

SC_FS_CUR_0

F9

I

Standalone mode configuration, Fullstep mode current, bit 0

SC_FS_CUR_1

G9

I

Standalone mode configuration, Fullstep mode current, bit 1

SC_FS_THRS_0

E8

I

Standalone mode configuration, Fullstep mode threshold, bit 0

SC_FS_THRS_1

F8

I

Standalone mode configuration, Fullstep mode threshold, bit 1

SC_FS_THRS_2

G8

I

Standalone mode configuration, Fullstep mode threshold, bit 2

SC_P_REG_CUR_0

J9

I

Standalone mode configuration, Current regulator target, bit 0

SC_P_REG_CUR_1

K9

I

Standalone mode configuration, Current regulator target, bit 1