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OMAP-L138 Datasheet(PDF) 1 Page - Texas Instruments

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Part # OMAP-L138
Description  OMAP-L138 Low-Power Applications Processor
Download  268 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OMAP-L138 Datasheet(HTML) 1 Page - Texas Instruments

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1
OMAP-L138 Low-Power Applications Processor
1.1 Features
OMAP-L138 Low-Power Applications Processor
www.ti.com
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
(RCPxP) and Square-Root Reciprocal
• Dual Core SoC
Approximation (RSQRxP) Operations
300-MHz ARM926EJ-S™ RISC MPU
Per Cycle
300-MHz C674x VLIW DSP
Two Multiply Functional Units
• ARM926EJ-S Core
• Mixed-Precision IEEE Floating Point
32-Bit and 16-Bit (Thumb®) Instructions
Multiply Supported up to:
DSP Instruction Extensions
2 SP x SP -> SP Per Clock
Single Cycle MAC
2 SP x SP -> DP Every Two Clocks
ARM® Jazelle® Technology
2 SP x DP -> DP Every Three Clocks
EmbeddedICE-RT™ for Real-Time Debug
2 DP x DP -> DP Every Four Clocks
• ARM9 Memory Architecture
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
• C674x Instruction Set Features
Multiplies, or Eight 8 x 8-Bit Multiplies
Superset of the C67x+™ and C64x+™ ISAs
per Clock Cycle, and Complex Multiples
2400/1800 C674x MIPS/MFLOPS
Instruction Packing Reduces Code Size
Byte-Addressable (8-/16-/32-/64-Bit Data)
All Instructions Conditional
8-Bit Overflow Protection
Hardware Support for Modulo Loop
Bit-Field Extract, Set, Clear
Operation
Normalization, Saturation, Bit-Counting
Protected Mode Operation
Compact 16-Bit Instructions
Exceptions Support for Error Detection and
• C674x Two Level Cache Memory Architecture
Program Redirection
32K-Byte L1P Program RAM/Cache
• Software Support
32K-Byte L1D Data RAM/Cache
TI DSP/BIOS™
256K-Byte L2 Unified Mapped RAM/Cache
Chip Support Library and DSP Library
Flexible RAM/Cache Partition (L1 and L2)
• 128K-Byte RAM Shared Memory
1024K-Byte Boot ROM
• 1.8V or 3.3V LVCMOS IOs (except for USB and
• Enhanced Direct-Memory-Access Controller 3
DDR2 interfaces)
(EDMA3):
• Two External Memory Interfaces:
2 Channel Controllers
EMIFA
3 Transfer Controllers
• NOR (8-/16-Bit-Wide Data)
64 Independent DMA Channels
• NAND (8-/16-Bit-Wide Data)
16 Quick DMA Channels
• 16-Bit SDRAM With 128 MB Address
Programmable Transfer Burst Size
Space
• TMS320C674x Floating-Point VLIW DSP Core
DDR2/Mobile DDR Memory Controller
Load-Store Architecture With Non-Aligned
• 16-Bit DDR2 SDRAM With 512 MB
Support
Address Space or
64 General-Purpose Registers (32 Bit)
• 16-Bit mDDR SDRAM With 256 MB
Six ALU (32-/40-Bit) Functional Units
Address Space
• Supports 32-Bit Integer, SP (IEEE Single
• Three Configurable 16550 type UART Modules:
Precision/32-Bit) and DP (IEEE Double
With Modem Control Signals
Precision/64-Bit) Floating Point
16-byte FIFO
• Supports up to Four SP Additions Per
16x or 13x Oversampling Option
Clock, Four DP Additions Every 2
• LCD Controller
Clocks
• Supports up to Two Floating Point (SP
• Two Serial Peripheral Interfaces (SPI) Each
or DP) Reciprocal Approximation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C6000, C6000 are trademarks of Texas Instruments.
ARM926EJ-S is a trademark of ARM Limited.
PRODUCT PREVIEW information concerns products in the
Copyright © 2009–2009, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.


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