74HCT9046AN datasheet(6/43 Pages) NXP

Part #	74HCT9046AN

Description	PLL with band gap controlled VCO

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74HCT9046A_6

Product data sheet

Rev. 06 — 15 September 2009

6 of 43

NXP Semiconductors

74HCT9046A

PLL with band gap controlled VCO

8.

Functional description

The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two

different phase comparators (PC1 and PC2) with a common signal input ampliﬁer and a

common comparator input, see Figure 1. The signal input can be directly coupled to large

voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage signals within the linear region

of the input ampliﬁers. With a passive low-pass ﬁlter, the 74HCT9046A forms a

second-order loop PLL.

The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However

extra features are built-in, allowing very high-performance phase-locked-loop applications.

This is done, at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is

equipped with a current source output stage here. Further a band gap is applied for all

internal references, allowing a small center frequency tolerance. The details are summed

up in Section 8.1. If one is familiar with the 74HCT4046A already, it will do to read this

section only.

8.1 Differences with respect to the familiar 74HCT4046A

• A center frequency tolerance of maximum

±10 %.

• The on board band gap sets the internal references resulting in a minimal frequency

shift at supply voltage variations and temperature variations.

• The value of the frequency offset is determined by an internal reference voltage of

2.5 V instead of VCC − 0.7 V; In this way the offset frequency will not shift over the

supply voltage range.

• A current switch charge pump output on pin PC2_OUT allows a virtually ideal

performance of PC2; The gain of PC2 is independent of the voltage across the

low-pass ﬁlter; Further a passive low-pass ﬁlter in the loop achieves an active

performance. The inﬂuence of the parasitic capacitance of the PC2 output plays no

role here, resulting in a true correspondence of the output correction pulse and the

phase difference even up to phase differences as small as a few nanoseconds.

• Because of its linear performance without dead zone, higher impedance values for the

ﬁlter, hence lower C-values, can be chosen; correct operation will not be inﬂuenced by

parasitic capacitances as in case of the voltage source output using the

74HCT4046A.

• No PC3 on pin RB but instead a resistor connected to GND, which sets the

load/unload currents of the charge pump (PC2).

• Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz

and higher.

• Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to VCC (no

bias resistor Rbias) pin PC1_OUT/PCP_OUT has its familiar function viz. output of

PC1. If at pin RB a resistor (Rbias) is connected to GND it is assumed that PC2 has

been chosen as phase comparator. Connection of Rbias is sensed by internal circuitry

and this changes the function of pin PC1_OUT/PCP_OUT into a lock detect output

(PCP_OUT) with the same characteristics as PCP_OUT of pin 1 of the 74HCT4046A.

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