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TMS320DM6467CZUT Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320DM6467CZUT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 357 page  TMS320DM6467 Digital Media System-on-Chip SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009 www.ti.com Table 3-1. Characteristics of the DM6467 Processor (continued) HARDWARE FEATURES DM6467 Size (Bytes) 248KB RAM, 8KB ROM DSP • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 128KB Unified Mapped RAM/Cache (L2) On-Chip Memory Organization ARM • 16KB I-cache • 8KB D-cache • 32KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 C64x+ Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision (address location: 0x0181 2000) JTAGID Register See Section 7.29.1, JTAG ID (JTAGID) Register JTAG BSDL_ID (address location: 0x01C4 0028) Description(s) DSP 594 MHz (-594) DSP 729 MHz (-729) CPU Frequency MHz ARM926 297 MHz(-594) ARM926 364.5 MHz(-729) DSP 1.68 ns (-594) DSP 1.37 ns (-729) Cycle Time ns ARM926 3.37 ns (-594) ARM926 2.74 ns (-729) Normal 1.2 V (-594, -594A, -729, -729D) Core (V) 1.2 V (-594V, -594AV) SmartReflex Voltage (see Table 4-39) 1.05 V (-594V, -594AV) I/O (V) 1.8 V, 3.3 V (-594, -729) DEV_CLKIN frequency multiplier (PLLC1) x1 (Bypass), x14 to x22 (-594) (27-MHz reference) x1 (Bypass), x14 to x27 (-729) PLL Options DEV_CLKIN frequency multiplier (PLLC2) x1 (Bypass), x14 to x22 (-594) (27-MHz reference) x1 (Bypass), x14 to x23 (-729) AUX_CLKIN frequency 24/48-MHz reference BGA Package 19 x 19 mm 529-Pin BGA (ZUT) Process Technology µm 0.09 µm Product Preview (PP), Product Status(1) Advance Information (AI), PD or Production Data (PD) (1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Overview 10 Submit Documentation Feedback |
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