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TMS320DM647 Datasheet(PDF) 11 Page - Texas Instruments

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Part # TMS320DM647
Description  Digital Media Processor
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS320DM647 Datasheet(HTML) 11 Page - Texas Instruments

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TMS320DM647
TMS320DM648
www.ti.com
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
2.3
C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P)
consists of 32KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 data memory/cache (L1D) consists of 32KB that can be configured as mapped memory or 2-way
associated cache. The Level 2 memory/cache (L2) consists of a 256KB (DM647)/512 KB (DM648)
memory space that is shared between program and data space. L2 memory can be configured as mapped
memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
Table 2-2. C64x+ Cache Registers
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x0184 0000
L2CFG
L2 cache configuration register
0x0184 0020
L1PCFG
L1P size cache configuration register
0x0184 0024
L1PCC
L1P freeze mode cache configuration register
0x0184 0040
L1DCFG
L1D size cache configuration register
0x0184 0044
L1DCC
L1D freeze mode cache configuration register
0x0184 0048 - 0x0184 0FFC
-
Reserved
0x0184 1000
-
Reserved
0x0184 1004 - 0x0184 1FFC
-
Reserved
0x0184 2000
L2ALLOC0
L2 allocation register 0
0x0184 2004
L2ALLOC1
L2 allocation register 1
0x0184 2008
L2ALLOC2
L2 allocation register 2
0x0184 200C
L2ALLOC3
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
-
Reserved
0x0184 4000
L2WBAR
L2 writeback base address register
0x0184 4004
L2WWC
L2 writeback word count register
0x0184 4010
L2WIBAR
L2 writeback invalidate base address register
0x0184 4014
L2WIWC
L2 writeback invalidate word count register
0x0184 4018
L2IBAR
L2 invalidate base address register
0x0184 401C
L2IWC
L2 invalidate word count register
0x0184 4020
L1PIBAR
L1P invalidate base address register
0x0184 4024
L1PIWC
L1P invalidate word count register
0x0184 4030
L1DWIBAR
L1D writeback invalidate base address register
0x0184 4034
L1DWIWC
L1D writeback invalidate word count register
0x0184 4038
-
Reserved
0x0184 4040
L1DWBAR
L1D block writeback
0x0184 4044
L1DWWC
L1D block writeback
0x0184 4048
L1DIBAR
L1D invalidate base address register
0x0184 404C
L1DIWC
L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF
-
Reserved
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2 writeback invalidate all register
0x0184 5008
L2INV
L2 global invalidate without writeback
0x0184 500C - 0x0184 5027
-
Reserved
0x0184 5028
L1PINV
L1P global invalidate
0x0184 502C - 0x0184 5039
-
Reserved
0x0184 5040
L1DWB
L1D global writeback
0x0184 5044
L1DWBINV
L1D global writeback with invalidate
0x0184 5048
L1DINV
L1D global invalidate without writeback
Copyright © 2010–2009, Texas Instruments Incorporated
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