74LVC1G175_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 21 May 2007

3 of 17

NXP Semiconductors

74LVC1G175

Single D-type flip-flop with reset; positive-edge trigger

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;

↑ = LOW-to-HIGH CP transition;

X = don’t care.

Fig 4.

Pin configuration SOT363

and SOT457

Fig 5.

Pin configuration SOT886

Fig 6.

Pin configuration SOT891

74LVC1G175

CP

MR

GND

DQ

001aag506

1

2

3

6

5

4

74LVC1G175

GND

001aag507

CP

D

MR

Q

Transparent top view

2

3

1

5

4

6

74LVC1G175

GND

001aag508

CP

D

MR

Q

Transparent top view

2

3

1

5

4

6

Table 3.

Pin description

Symbol

Pin

Description

CP

1

clock input (LOW-to-HIGH, edge-triggered)

GND

2

ground (0 V)

D

3

data input

Q

4

flip-flop output

5

supply voltage

MR

6

master reset input (active LOW)

Table 4.

Function table[1]

Operating mode

Input

Output

MR

CP

D

Q

Reset (clear)

L

X

X

L

Load ‘1’

H

↑

hH

Load ‘0’

H

↑

lL