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74LVT241D Datasheet(PDF) 9 Page - NXP Semiconductors |
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74LVT241D Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74LVT241_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 May 2008 9 of 16 NXP Semiconductors 74LVT241 3.3 V octal buffer/line driver; 3-state Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Test circuit for switching times VEXT VCC VI VO 001aae235 DUT CL RT RL RL PULSE GENERATOR VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf Table 9. Test data Input Load VEXT VI fi tW tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF GND 6 V open |
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