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NCP4303ADR2G Datasheet(PDF) 5 Page - ON Semiconductor |
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NCP4303ADR2G Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 26 page NCP4303A/B http://onsemi.com 5 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low=−1 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCC_on Turn−on threshold level (VCC going up) 1 9.3 9.9 10.5 V VCC_off Minimum operating voltage after turn−on (VCC going down) 1 8.3 8.9 9.5 V VCC_hyste VCC hysteresis 1 0.8 1.0 1.3 V ICC1_A ICC1_B Internal IC consumption (no output load on pin 8, Fsw = 500 kHz, RTon_min = RToff_min = 5 kW) 1 − − 4.7 4 − − mA ICC2_A ICC2_B Internal IC consumption (Cload = 1 nF on pin 8, Fsw = 400 kHz, RTon_min = RToff_min = 5 kW) 1 − − 9.3 6.4 − − mA ICC3_A ICC3_B Internal IC consumption (Cload = 10 nF on pin 8, Fsw = 400 kHz, RTon_min = RToff_min = 5 kW) 1 − − 54 34 − − mA ICC_SDM Startup current consumption (VCC = VCC_on − 0.1 V) and consumption during light load (disable) mode, (Fsw = 500 kHz, Vtrig = 5 V) 1 − 390 550 mA ICC_SDM NS Startup current consumption (VCC = VCC_on − 0.1 V) and consumption during light load (disable) mode, (Vcs = 0 V, Vtrig = 5 V) 1 − 280 450 mA DRIVE OUTPUT tr_A Output voltage rise−time for A version (Cload = 10 nF), (Note 3) 8 − 120 − ns tr_B Output voltage rise−time for B version (Cload = 10 nF), (Note 3) 8 − 80 − ns tf_A Output voltage fall−time for A version (Cload = 10 nF), (Note 3) 8 − 50 − ns tf_B Output voltage fall−time for B version (Cload = 10 nF), (Note 3) 8 − 35 − ns Roh Driver source resistance (Note 3) 8 − 1.8 7 W Rol Driver sink resistance 8 − 1 2 W IDRV_pk(source) Output source peak current (Note 3) 8 − 2.5 − A IDRV_pk(sink) Output sink peak current (Note 3) 8 − 5 − A VDRV(H)_A Driver high level output voltage on A version (Cload = 1 nF) 8 10 − − V VDRV(H)_A Driver high level output voltage on A version (Cload = 10 nF) 8 11.8 − − V VDRV(H)_B Driver high level output voltage on B version (Cload = 1 nF) 8 5 − − V VDRV(H)_B Driver high level output voltage on B version (Cload = 10 nF) 8 6 − − V VDRV(min_A) Minimum drive output voltage for A version (VCC = VCC_off + 200 mV) 8 8.3 − − V VDRV(min_B) Minimum drive output voltage for B version (VCC = VCC_off + 200 mV) 8 4.5 − − V VDRV(CLMP_A) Driver clamp voltage for A version, (12 V < VCC < 28 V, minimum Cload = 1 nF) 8 − 12 16 V VDRV(CLMP_B) Driver clamp voltage for B version, (12 V < VCC < 28 V, minimum Cload = 1 nF) 8 − 7 8.3 V CS INPUT Tpd_on The total propagation delay from CS input to DRV output turn on (VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND) 5, 8 − 60 90 ns Tpd_off The total propagation delay from CS input to DRV output turn off (VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND), (Note 3) 5, 8 − 40 55 ns Ishift_CS Current sense input current source (VCS = 0 V) 5 95 100 105 mA Vth_cs_on Turn on current sense input threshold voltage 5, 8 −120 −85 −50 mV Vth_cs_off Current sense pin turn off threshold voltage, COMP pin connected to GND (Note 3) 5, 8 −1 − 0 mV Gcomp Compensation inverter gain (Note 3) 5,6,8 − −1 − − 3. Guaranteed by design. |
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